FPGA code

This software comes in two flavors.

Flavor one consists of the code that tells the FPGA how to behave. This code is mostly Verilog, is compiled in Altera’s Quartus II 12.1 sp1 (at the moment), and consists of essentially two bits – a “soft” CPU called Nios (also from Altera, comes as a core¬†with user settings), and a number of identical SmrDriver modules, each of which can talk to the CPU and have its parameters set individually.¬† A single SmrDriver will typically be in charge of controlling a single resonator.

Flavor two consists of the code that runs on the Nios CPU. This is almost all in C, is mostly auto-generated via Altera’s IDE for Nios (called “Nios II Software Build Tools”, basically a modified version of Eclipse). This code is responsible for (A) accepting and maintaining the TCP connection with the PC, (B) setting SmrDriver parameters when the PC tells it to, (C) reading SmrDriver parameters when the PC tells it to, and (D) sending SmrDriver data (typically the resonator’s resonant frequency or amplitude) to the PC.

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