SmrDriverClient is the VI that allows you to set any parameter for any SmrDriver. It connects the FPGA via TCP.

It also contains a queue that allows you to either request all the current SmrDriver parameters (alternatively, call, which will call this queue for you), or set SmrDriver  parameters.

Its parameters are as follows:

RunIf this is off, the SmrDriver doesnt run. toggling this on and off resets most of the SmrDriver (except for its registers).
Send data to PCSend data over ethernet to the PC? (should generally be on)
Run NCO at fixed freqMisnomer. Means force the PLL to generate a drive signal at the desired frequency (the frequency parameter below), instead of tracking the input frequency.
Input sourceUse input from adc_a or adc_b?
DAC_A outputWhat should be sent to output a?
DAC_B outputWhat should be sent to output b?
Signal of interestWhich signal should the FPGA send to the computer over UDP (Multicast)?
FrequencyThis controls several things. If you turn run on and off and back on, the PLL will reset to this frequency. If "Run NCO at fixed freq" is selected, then this is the frequency that will be used. This is also the reference frequency if you're operating a device in direct feedback and measuring the frequency via mixing down to a lower frequency.
cic_rateCIC refers to a cascaded integrator comb filter, a decimating which is used in each SmrDriver. This parameter sets the filter width, and thus controls the decimation factor. The maximum value this parameter can take is 32767, and it should not be reduced below probably 256 or so.

Note that this sets the datarate for the signal of interest (except for in the case of "PLL frequency", which is subject to an additional optional decimation). If the CIC rate is 32767, the datarate will be 100 MHz/32767, which is about 3051 Hz. If the CIC rate is 1000, the datarate will be 100 kHz (which may be unacceptably high).
cic_shiftThis is a gain, implemented as a bit shift. Therefore every change of 1 here changes the CIC filter output by a factor of 2. Because the CIC filter has a gain that depends on its rate, we shift off bits to compensate for this gain. A full-scale input at a CIC rate of 32767 should have a bit shift of 24. If the input amplitude is halved, the bit shift should be 23 to ensure a full-scale output. Every time the CIC rate is reduced two-fold, the CIC shift should be reduced by 2 (because the CIC is a 2nd-order filter, and therefore a 2x change in the rate causes a 4x change in the gain. 4x = 2 bits.)
feedback delayThis is in units of 10s of nanoseconds, and is the phase-shift applied to the output choice "Feedback". Fractional feedback delays are possible via interpolation - e.g. a feedback delay of 13.4 would amount to a 134 ns delay. This value can range from 0 to 1024.
feedback gainThis value is a 8.8 fixed point, and therefore can range between 0 and 256, with a minimum non-zero value of 1/256.
pll datarate decimationThis is an additional averaging decimation factor applied to the 'PLL frequency' datastream only. For example, if the CIC rate is 25000, then the datarate would natively be 100 MHz/25000 = 4 kHz. However, by setting the decimation factor to 8, every 8 datapoints are averaged on the FPGA and data is transmitted from the FPGA to the PC at 500 Hz.
minimum frequency, maximum frequency.When "Run NCO at fixed frequency" is not selected, the PLL will try to lock to a signal within these bounds.
Resonator Q, Loop Order, and Loop BandwidthThe goal is that the PLL-resonator system will have a transfer function that is a Butterworth filter with a user-specified order and a user-specified bandwidth. The Q of the resonator is needed to calculate PLL gains to achieve this goal. If the Q is not correctly set, the measurement bandwidth may differ significantly from the target bandwidth.
PLL delayRanges from 0 to 1, represented as a 0.16 fixed point. 0 and 1 represent 0 and 360 degrees.
PLL drive amplitudeRanges from 0 to 1, 14-bit resolution. 1 is full-scale output from the DAC.
ImpulseWhen this transitions from low to high, the PLL is kicked out of lock by 10 degrees. The response to this perturbation can be used to measure the frequency measurement bandwidth and transfer function.
Enable AGCShould be on. Generally wouldn't want to change this.
Restart all PLLs in closed loopBuggy - not recommended.

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